A conventional four-transistor (4T) RAM cell consists of a two transistor, two resistive-load cross-coupled inverters plus two access transistors (also known as wordline, transfer gate, or pass-gate transistors), such as described in S. M. Sze, VLSI Technology, McGraw-Hill, New York, pp. 473-478 (1983). The two transistors in the cross-coupled inverter, are known as driver or pull-down transistors. These transistors act as switches wherein current flow from the drain to source regions is controlled by the voltage on the gate region. Referring to FIG. 1, two nodes exist in the cell: node 1 connects one load, the drain of one pass-gate transistor, T2, the drain of one driver transistor, T1, and the gate of the other driver transistor T3. Node 2 connects the other load, the drain of the other pass-gate transistor, T4, the drain of T3, and the gate of T1. These two nodes are the storage nodes of the memory cell and must achieve stable logic values during standby and during cell reading for reliable operation.
In such cells, data retention reliability is a direct function of cell stability and noise margin. This noise margin is measured by how well one driver transistor, T1, holds a low logic level. This low level must remain below the threshold voltage of the other driver transistor, T3, to insure that T3 is off, and therefore to prevent the from flipping. This condition is known as bistability and implies that the two storage nodes of the cell achieve valid logic values, one being a logic high and the other a logic low. These levels are maintained due to the feedback in the cross-coupled inverter. If node 1 exceeds the threshold of T3, then T3 will conduct and easily degrade the high level on node 2. This condition results in unstable operation if the leakage current in T3 exceeds the current supplying capability of the load means 28. Unstable operation means that the cell will change state.
The worst case for cell logic low level is during the time the word line is being selected and the transfer gate, T2, begins to pull up against TI. A good logic low on node 1, and therefore good noise margin and stability, is achieved by making T2 small with respect to T1. However, the speed with which the cell develops differential to the sense amp during read is determined by the rate at which the bit line capacitance is discharged through the T2, T1 pair and therefore by the size of the transfer gate, T2 (W/L). For high cell pull current, T2 should be sized large with respect to T1, High cell pull current results in fast cell read access time, since that current is responsible for slewing the bit-line capacitance and developing differential to the sense amp. The sense amp is a differential amplifier whose inputs are BIT and BIT.
These conflicting transfer gate sizing requirements for speed and stability limit the ultimate performance of the traditional cell configuration. The cell must be designed to meet a minimum stability level for reliable operation over process variations and operating conditions. Once stability is designed for, cell pull current is fixed and cannot be increased.
This problem is exacerbated in enhancement/depletion mode GaAs RAM design, since the enhancement FET threshold voltage has a strong dependence on temperature and drops significantly at elevated operating temperatures This forces the transfer gate to further decrease in size to maintain cell stability over wide temperature ranges. This decreased size slows down the cell read access time.
Thus, the conventional approach is drastically limited in flexibility to address this tradeoff of speed versus stability. Many static RAM manufacturers have simply decreased the pull-down driver to transfer gate ratio to get improved cell speed, but as a result are plagued with marginally stable cells and "weak bits" which are hard to detect and test. Typical ratios of pull-down size to transfer gate are between three and five (in terms of W/L).
The only other alternative to speeding up the cell is to maintain an adequate cell ratio for stability and then scale FET sizes up to get increased cell pull current. However, this increases chip size and power and is only marginally effective, since the load capacitance the cell must drive scales with cell size as well. There may be no real improvement in cell speed by this method.
Thus, it is desired to achieve both high speed and stability in a GaAs static RAM cell, without having to compromise one or the other property.